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K4F661612B,K4F641612B
CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
* Part Identification - K4F661612B-TC/L(3.3V, 8K Ref., TSOP) - K4F641612B-TC/L(3.3V, 4K Ref., TSOP)
* Fast Page Mode operation * 2CAS Byte/Word Read/Write operation * CAS-before-RAS refresh capability * RAS-only and Hidden refresh capability * Self-refresh capability (L-ver only) * Fast parallel test mode capability * LVTTL(3.3V) compatible inputs and outputs Unit : mW * Early Write or output enable controlled write * JEDEC Standard pinout * Available in Plastic TSOP(II) packages * +3.3V0.3V power supply 4K 468 432 396
* Active Power Dissipation Speed -45 -50 -60 * Refresh Cycles Part NO. K4F661612B* K4F641612B Refresh cycle 8K 4K Refresh time Normal 64ms L-ver 128ms
RAS UCAS LCAS W
8K 360 324 288
FUNCTIONAL BLOCK DIAGRAM
Control Clocks Vcc Vss Lower Data in Buffer Sense Amps & I/O Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer
VBB Generator
* Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Refresh Timer Refresh Control Refresh Counter
Row Decoder
DQ0 to DQ7
* Performance Range Speed -45 -50 -60
Memory Array 4,194,304 x 16 Cells
OE DQ8 to DQ15
tRAC
45ns 50ns 60ns
tCAC
12ns 13ns 15ns
tRC
80ns 90ns 110ns
tPC
31ns 35ns 40ns
A0~A12 (A0~A11)*1 A0~A8 (A0~A9)*1
Row Address Buffer Col. Address Buffer Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
K4F661612B,K4F641612B
CMOS DRAM
PIN CONFIGURATION (Top Views)
* K4F661612B-T * K4F641612B-T VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C VSS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
(400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product
Pin Name A0 - A12 A0 - A11 DQ0 - 15 VSS RAS UCAS LCAS W OE VCC N.C
Pin function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Data Output Enable Power(+3.3V) No Connection
K4F661612B,K4F641612B
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT VCC Tstg PD IOS Address Rating -0.5 to +6.5 -0.5 to +4.6 -55 to +150 1 50
CMOS DRAM
Units V V C W mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3 *2 Typ 3.3 0 Max 3.6 0 +5.5*1 0.8 Units V V V V
*1 : 6.5V at pulse width 15ns which is measured at VCC *2 : -1.3 at pulse width 15ns which is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVCC+0.3V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V
K4F661612B,K4F641612B
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed -45 -50 -60 Dont care -45 -50 -60 -45 -50 -60 Dont care -45 -50 -60 Dont care Dont care Max K4F661612B 100 90 80 2 2 100 90 80 70 60 50 500 300 100 90 80 400 400 K4F641612B 130 120 110 2 2 130 120 110 80 70 60 500 300 130 120 110 400 400
CMOS DRAM
Units mA mA mA mA mA mA mA mA mA mA mA uA uA mA mA mA uA uA
ICC1
Dont care Normal L Dont care
ICC2
ICC3
ICC4
Dont care Normal L Dont care L L
ICC5
ICC6 ICC7 ICCS
ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V, W, OE=VIH, Address=Dont care DQ=Open, TRC=31.25us ICCS : Self Refresh Current RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.
K4F661612B,K4F641612B
CAPACITANCE (TA=25C, VCC=3.3V, f=1MHz)
Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, UCAS, LCAS, W, OE] Output capacitance [DQ0 - DQ15] Symbol CIN1 CIN2 CDQ Min -
CMOS DRAM
Max 5 7 7 Units pF pF pF
AC CHARACTERISTICS (0CTA70C, See note 1,2)
Test condition : VCC=3.3V0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Symbol Min -45 Max Min 90 133 45 12 23 0 0 1 25 45 12 45 12 18 13 5 0 8 0 8 23 0 0 0 8 8 13 12 0 10 10K 33 22 10K 13 50 0 0 1 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 0 10 10 15 13 0 10 10K 37 25 10K 13 50 50 13 25 0 0 1 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 0 10 10K 45 30 10K 13 50 -50 Max Min 110 153 60 15 30 -60 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16 9,19 9,19 8 8 13 13 4 10 3,4,10 3,4,5 3,10 3 6 2 Units Note
tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH
80 115
K4F661612B,K4F641612B
AC CHARACTERISTICS (Continued)
Parameter Refresh period (Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast Page mode cycle time Fast Page mode read-modify-write cycle time CAS precharge time (Fast page cycle) RAS pulse width (Fast page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Symbol Min -45 Max 64 128 0 32 67 43 48 5 10 5 26 31 70 9 45 28 12 12 0 12 10 15 10 10 100 80 -50 13 13 0 13 10 15 10 10 100 90 -50 13 200K 35 76 10 50 30 13 13 0 15 10 15 10 10 100 110 -50 200K 0 36 73 48 53 5 10 5 30 40 85 10 60 35 Min -50 Max 64 128 0 38 83 53 60 5 10 5 Min -60
CMOS DRAM
Units Max 64 128 ms ms ns ns ns ns ns ns ns ns 35 ns ns ns ns
Note
tREF tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tRASS tRPS tCHS
7 7,15 7 7
17 18
3
14
200K
ns ns
15
ns ns
13
ns ns ns ns ns ns us ns ns
6
11 11
20,21,22 20,21,22 20,21,22
K4F661612B,K4F641612B
TEST MODE CYCLE
Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time CAS to W delay time RAS to W delay time Column Address to W delay time Fast Page mode cycle time Fast Page mode read-modify-write cycle time RAS pulse width (Fast page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -45 Max Min 95 138 50 17 28 50 17 17 50 28 37 72 48 36 75 50 200K 31 17 17 17 18 18 10K 10K 55 18 18 55 30 41 78 53 40 81 55 200K 35 18 18 20 55 18 30 10K 10K 65 20 20 65 35 43 88 58 45 90 65 -50 Max Min 115 160 -60
CMOS DRAM
( Note 11 )
Units Max ns ns 65 20 35 10K 10K ns ns ns ns ns ns ns ns ns ns ns ns ns 200K 40 20 ns ns ns ns ns 3 7 7 7 3,4,10,12 3,4,5,12 3,10,12 Note
tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tPC tPRWC tRASP tCPA tOEA tOED tOEH
85 120
K4F661612B,K4F641612B
NOTES
CMOS DRAM
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL load and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min) and tAWDtAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. 10. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. These specifications are applied in the test mode. 11. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters 12. should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
K4F64(6)1612B Truth Table
RAS H L L L L L L L L LCAS X H L H L L H L L UCAS X H H L L H L L L W X X H H H L L L H OE X X L L L H H H H DQ0 - DQ7 Hi-Z Hi-Z DQ-OUT Hi-Z DQ-OUT DQ-IN DQ-IN Hi-Z DQ8-DQ15 Hi-Z Hi-Z Hi-Z DQ-OUT DQ-OUT DQ-IN DQ-IN Hi-Z STATE Standby Refresh Byte Read Byte Read Word Read Byte Write Byte Write Word Write -
K4F661612B,K4F641612B
13. tASC, tCAH are referenced to the earlier CAS falling edge.
CMOS DRAM
14. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle. 15. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle. 16. tCWL is specified from W falling edge to the earlier CAS rising edge. 17. tCSR is referenced to the earlier CAS falling edge before RAS transition low. 18. tCHR is referenced to the later CAS rising edge after RAS transition low.
RAS
LCAS
UCAS
tCSR
tCHR
19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge.
LCAS UCAS
tDS
DQ0 ~ DQ15 Din
tDH
20. If tRASS100us, then RAS precharge time must use tRPS instead of tRP. 21. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 22. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
K4F661612B,K4F641612B
WORD READ CYCLE
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS tCSH tRCD tRSH tCAS tCRP tCRP
tCRP
LCAS VIH VIL -
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH
tAA
OE VIH VIL -
tOEA tCAC tCLZ tOFF tOEZ
DATA-OUT
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL -
tRAC OPEN
tCAC tRAC OPEN tCLZ tOEZ
DATA-OUT
tOFF
Dont care Undefined
K4F661612B,K4F641612B
LOWER BYTE READ CYCLE
NOTE : DIN = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRPC
tCRP
LCAS VIH VIL -
tCSH tRCD tRAD tRSH tCAS
tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH tOFF tAA tOEZ tOEA tCAC tCLZ
DATA-OUT
OE
VIH VIL -
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL -
tRAC OPEN
OPEN
Dont care Undefined
K4F661612B,K4F641612B
UPPER BYTE READ CYCLE
NOTE : DIN = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS tRPC tCRP
tCRP
LCAS VIH VIL -
tRAD tRAL tASR tRAH tASC tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH tOFF tAA tOEZ tOEA
OE
VIH VIL -
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL -
OPEN tCAC tRAC OPEN tCLZ
DATA-OUT
Dont care Undefined
K4F661612B,K4F641612B
WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS tCSH tRCD tRSH tCAS tCRP tCRP
tCRP
LCAS VIH VIL -
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
DQ0 ~ DQ7 VIH VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRPC
tCRP
LCAS VIH VIL -
tCSH tRCD tRSH tCAS tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
DQ0 ~ DQ7 VIH VIL -
tDS
tDH
DATA-IN
DQ8 ~ DQ15 VIH VIL -
Dont care Undefined
K4F661612B,K4F641612B
UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRAS
RAS VIH VIL -
tRC
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS
tCRP
tCRP
LCAS VIH VIL -
tRPC
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
DQ0 ~ DQ7 VIH VIL -
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
WORD WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRAS
RAS VIH VIL -
tRC
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS tCSH tRCD tRSH tCAS tCRP tCRP
tCRP
LCAS VIH VIL -
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tRWL
W VIH VIL -
tWP
OE
VIH VIL -
tOED tDS
tOEH tDH
DATA-IN
DQ0 ~ DQ7 VIH VIL -
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRAS
RAS VIH VIL -
tRC
tRP
tCRP
UCAS VIH VIL -
tRPC
tCRP
LCAS VIH VIL -
tCSH tRCD tRSH tCAS tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL tRWL
W VIH VIL -
tWP
OE
VIH VIL -
tOED tDS
tOEH tDH
DATA-IN
DQ0 ~ DQ7 VIH VIL -
DQ8 ~ DQ15 VIH VIL -
Dont care Undefined
K4F661612B,K4F641612B
UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tCSH tRCD tRSH tCAS tCRP
tCRP
LCAS VIH VIL -
tRPC
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tCWL
W VIH VIL -
tRWL tWP
OE
VIH VIL -
tOED
tOEH
DQ0 ~ DQ7 VIH VIL -
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
WORD READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRCD
tRSH tCAS
tCRP
LCAS VIH VIL -
tRCD tRAD
tRSH tCAS tCSH
tASR
A VIH VIL -
tRAH
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
tAWD tCWD
W VIH VIL VIH VIL -
tRWL tCWL tWP
tRWD tOEA tCLZ tCAC tAA tOED tOEZ
VALID DATA-OUT
OE
DQ0 ~ DQ7 VI/OH VI/OL -
tRAC
tDS
tDH
VALID DATA-IN
tCLZ tCAC
DQ8 ~ DQ15 VI/OH VI/OL -
tAA tRAC
tOED tOEZ
VALID DATA-OUT
tDS
tDH
VALID DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
LOWER-BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRPC
tCRP
LCAS VIH VIL -
tRCD tRAD
tRSH tCAS tCSH
tASR
A VIH VIL -
tRAH
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
tAWD tCWD
W VIH VIL VIH VIL -
tRWL tCWL tWP
tRWD tOEA tCLZ tCAC tAA tOED tOEZ
VALID DATA-OUT
OE
DQ0 ~ DQ7 VI/OH VI/OL DQ8 ~ DQ15 VI/OH VI/OL -
tRAC
tDS
tDH
VALID DATA-IN
OPEN
Dont care Undefined
K4F661612B,K4F641612B
UPPER-BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
UCAS VIH VIL -
tRCD
tRSH tCAS
tCRP
LCAS VIH VIL -
tRPC
tRAD tASR tRAH tASC tCAH tCSH
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
tAWD tCWD
W VIH VIL VIH VIL -
tRWL tCWL tWP
tRWD tOEA
OE
DQ0 ~ DQ7 VI/OH VI/OL -
OPEN tCLZ tCAC tAA tRAC tOED tOEZ
VALID DATA-OUT
DQ8 ~ DQ15 VI/OH VI/OL -
tDS
tDH
VALID DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
FAST PAGE MODE WORD READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL o
tRP
tCSH tCRP tRCD
UCAS VIH VIL -
tRHCP tPC tCAS tCP tPC tCAS tCP tPC tCAS tCP tCAS tRAL tRPC
tCRP tRCD
LCAS VIH VIL -
tCP tCAS tCAS
tCP tCAS
tCP tCAS
tRPC
tASR
A VIH VIL -
tRAD tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRCS
W VIH VIL -
tRCH
tRCS tRCH
tRCS tRCH
tRCS tRCH
tRRH
tCAC tAA tAA
OE VIH VIL -
tCAC tAA tCPA tOEA tAA tCPA tOEA
tCAC
tCPA tOEA
tOEA
tCAC
DQ0 ~ DQ7 VOH VOL -
tOFF tOEZ
VALID DATA-OUT VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tOFF tOEZ
tRAC
tCLZ tCAC
DQ8 ~ DQ15 VOH VOL -
tOFF tOEZ
VALID DATA-OUT VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tOFF tOEZ
tRAC
tCLZ
Dont care Undefined
K4F661612B,K4F641612B
FAST PAGE MODE LOWER BYTE READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL o
tRP
tRHCP tCRP
UCAS VIH VIL -
tRPC tCSH tRAL tPC tRCD tCAS tRAD tRAH tASC tCAH
COLUMN ADDRESS
tCRP
LCAS VIH VIL -
tPC tCP tCAS tCP
tPC tCP tCAS tCAS tRPC
tASR
A VIH VIL -
tASC tCAH
COLUMN ADDRESS
tASC
tCAH
COLUMN ADDR
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
tRCS
W VIH VIL -
tRCS tRCH tRCH
tRCS tRCH
tRCS tRCH
tRRH
tCAC tAA
VIH VIL -
tCAC tAA tCPA tOEA tAA tCPA tOEA
tCAC
tAA tOEA
tCPA tOEA
OE
DQ0 ~ DQ7 VOH VOL -
tCAC tRAC
VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tOFF tOEZ
tCLZ
DQ8 ~ DQ15 VOH VOL -
OPEN
Dont care Undefined
K4F661612B,K4F641612B
FAST PAGE MODE UPPER BYTE READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL o
tRP
tCSH tCRP
UCAS VIH VIL -
tRHCP tPC tCP tPC tCAS tCP tPC tCAS tCP tCAS tRPC
tRCD
tCAS
tCRP
LCAS VIH VIL -
tRPC tRAL tRAD tRAH tASC
tASR
A VIH VIL -
tCAH
tASC
tCAH
tASC
tCAH
COLUMN ADDR
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRCS
W VIH VIL -
tRCS tRCH tRCH
tRCS tRCH
tRCS tRCH
tRRH
tCAC tAA tOEA tAA tCPA tOEA tAA tCPA tOEA
tCAC tAA tCPA tOEA
tCAC
OE
VIH VIL -
DQ0 ~ DQ7 VOH VOL -
OPEN
DQ8 ~ DQ15 VOH VOL -
tCAC tRAC
VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tOFF tOEZ
VALID DATA-OUT
tOFF tOEZ
tCLZ
Dont care Undefined
K4F661612B,K4F641612B
FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
UCAS VIH VIL -
tPC tRCD tCAS tPC tRCD tCAS tRAD tCP tCAS
o
tPC tCP tCAS
o
tRSH tCP tCAS tCRP
tCRP
LCAS VIH VIL -
tPC tCP
tRSH tCAS tRAL
tASR
A VIH VIL -
tRAH
tCSH tASC
tCAH
tASC
tCAH
o o
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP
o
tWCS
tWCH tWP
tWP
OE
VIH VIL -
o o
DQ0 ~ DQ7 VIH VIL -
tDS
tDH
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
UCAS VIH VIL o
tRPC
tCRP
LCAS VIH VIL -
tPC tRCD tCAS tRAD tCP tCAS
o
tPC tCP
tRSH tCAS tRAL
tASR
A VIH VIL -
tRAH
tCSH tASC
tCAH
tASC
tCAH
o o
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP
o
tWCS
tWCH tWP
tWP
OE
VIH VIL -
o o
DQ0 ~ DQ7 VIH VIL -
tDS
tDH
VALID DATA-IN
tDS
tDH
VALID DATA-IN
tDS
o o
tDH
VALID DATA-IN
DQ8 ~ DQ15 VIH VIL -
Dont care Undefined
K4F661612B,K4F641612B
FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
UCAS VIH VIL -
tPC tRCD tCAS tCP tCAS
o
tPC tCP
tRSH tCAS tRPC
tCRP
LCAS VIH VIL -
tRAD tASR
A VIH VIL -
tRAH
tCSH tASC
tRAL tCAH tASC tCAH
o o
tASC
tCAH
ROW ADDR.
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH
tWCS
tWCH tWP
o
tWCS
tWCH tWP
tWP
OE
VIH VIL -
o o
DQ0 ~ DQ7 VIH VIL -
o o
DQ8 ~ DQ15 VIH VIL -
tDS
tDH
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
tDS
tDH
o
VALID DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP
tCSH tCRP tPRWC tRCD tCAS tCRP tRCD tCAS tRAD tRAH tASR tCAH tASC
COL. ADDR
tRSH tCP tCAS tCP tCAS tRAL tCAH tASC
COL. ADDR
tCRP
UCAS
VIH VIL -
tCRP
LCAS
VIH VIL -
A
VIH VIL -
ROW ADDR
tRCS tCWL
W VIH VIL -
tRCS tWP tCWD tAWD tCPWD tOEA
tRWL tCWL tWP
tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS
OE
VIH VIL -
tCAC tAA
tOED tDH tDS tOEZ
DQ0 ~ DQ7 VI/OH VI/OL -
tRAC tCLZ
tCLZ
VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN
DQ8 ~ DQ15 VI/OH VI/OL -
tOED tCAC tAA tOEZ tRAC tCLZ
tCAC tDH tDS tAA
tOED tDH tDS tOEZ
tCLZ
VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP
tCSH
tCRP
UCAS VIH VIL -
tRPC
tCRP
LCAS VIH VIL -
tRCD
tPRWC tCAS
tCP
tRSH tCAS
tCRP
tRAD tRAH tASR
A VIH VIL ROW ADDR
tCAH tASC
COL. ADDR
tRAL tASC
COL. ADDR
tCAH
tRCS
W VIH VIL -
tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS
tRCS tCWD tAWD tCPWD tOEA tCAC tAA tOED
tRWL tCWL tWP
OE
VIH VIL -
tDH tDS tOEZ
DQ0 ~ DQ7 VI/OH VI/OL -
tRAC tCLZ
tCLZ
VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN
DQ8 ~ DQ15 VI/OH VI/OL -
OPEN
Dont care Undefined
K4F661612B,K4F641612B
FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP
tCSH tCRP
tRCD
tPRWC tCAS
tCP
tRSH tCAS
tCRP
UCAS
VIH VIL -
tCRP
LCAS VIH VIL -
tRPC
tRAD tRAH tASR
A VIH VIL ROW ADDR
tCAH tASC
COL. ADDR
tRAL tASC
COL. ADDR
tCAH
tRCS
W VIH VIL -
tCWL tWP tCWD tAWD tRWD tOEA
tRCS tCWD tAWD tCPWD tOEA
tRWL tCWL tWP
OE
VIH VIL -
DQ0 ~ DQ7 VI/OH VI/OL -
OPEN tOED tCAC tAA tDH tOEZ tDS tCAC tAA tDH tOEZ tDS tOED
DQ8 ~ DQ15 VI/OH VI/OL -
tRAC tCLZ
tCLZ
VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
RAS - ONLY REFRESH CYCLE
NOTE : W, OE , DIN = Dont care DOUT = OPEN tRC
RAS VIH VIL -
CMOS DRAM
tRP tRPC
tRAS
tCRP
UCAS VIH VIL -
tCRP
LCAS VIH VIL -
tASR
A VIH VIL -
tRAH
ROW ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Dont care tRC tRAS tRPC tCSR tCHR
tRP
RAS VIH VIL -
tRP
tCRP tCP
UCAS
VIH VIL -
tCP
LCAS VIH VIL -
tCSR
tCHR
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL VIH VIL -
tOFF OPEN
OPEN tWRP tWRH
W
Dont care Undefined
K4F661612B,K4F641612B
HIDDEN REFRESH CYCLE ( READ )
CMOS DRAM
tRC
RAS VIH VIL -
tRP
tRC tRAS
tRP
tRAS
tCRP
UCAS VIH VIL -
tRCD
tRSH
tCHR
tCRP
LCAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR tRAH tASC
tRAL tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tRCS
W VIH VIL -
tWRH
tAA
OE VIH VIL -
tOEA tOFF
tCAC tCLZ
DQ0 ~ DQ7 VOH VOL -
tRAC OPEN
tOEZ
DATA-OUT
DQ8 ~ DQ15 VOH VOL -
OPEN
DATA-IN DATA-OUT
Dont care Undefined
K4F661612B,K4F641612B
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC
RAS VIH VIL -
tRP
tRC tRAS
tRP
tRAS
tCRP
UCAS VIH VIL -
tRCD
tRSH
tCHR
tCRP
LCAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tWRH
W VIH VIL -
tWCS tWP
tWRP tWCH
OE
VIH VIL -
DQ0 ~ DQ7 VIH VIL DQ8 ~ DQ15 VIH VIL -
tDS
tDH
DATA-IN
tDS
tDH
DATA-IN
Dont care Undefined
K4F661612B,K4F641612B
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE , A = Dont care tRP
RAS VIH VIL -
CMOS DRAM
tRASS
tRPS
tRPC tCP tCSR tCHS
tRPC
UCAS
VIH VIL -
tCP
LCAS VIH VIL -
tCSR
tCHS
DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL VIH VIL -
tOFF OPEN
OPEN tWRP tWRH
W
TEST MODE IN CYCLE
NOTE : OE , A = Dont care tRP
RAS VIH VIL -
tRC tRAS
tRP
tCRP tCP
UCAS VIH VIL -
tRPC tCSR tCHR
tCP
LCAS VIH VIL -
tCSR
tCHR
W
VIH VIL -
tWTS
tWTH
DQ0 ~ DQ15 VOH VOL -
tOFF OPEN
Dont care Undefined
K4F661612B,K4F641612B
PACKAGE DIMENSION
50 TSOP(II) 400mil
CMOS DRAM
Units : Inches (millimeters)
0.455 (11.56) 0.471 (11.96)
0.400 (10.16)
0.004 (0.10) 0.010 (0.25)
0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) MAX 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8
O
0.034 (0.875)
0.0315 (0.80)
0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45)

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